A summit on the state-of-play in FTQC
Fault-tolerant quantum computing (FTQC) is evolving fast, across a maze of architectures and approaches. That complexity makes it hard to get a clear view of where the field really stands.
To understand the current state-of-play in FTQC, alongside CEA, we gathered some of the brightest minds in the field for a week-long summit at the legendary Les Houches physics school.
The summit brought together students, researchers and leading experts from IBM, Amazon, Google, Yale, ETH Zürich, and more for a deep-dive into the latest research and strategies being explored in quantum error correction right now.
The goal? To bridge the gap between theory and hardware implementation, all while conquering alpine peaks in full Les Houches style.
Here’s Alice & Bob’s digest, a glimpse into some of the invited talks at the summit from:
- Harry Putterman (AWS)
- Barbara Terhal (Delft University of Technology)
- Theodore Yoder (IBM)
- Earl Campbell (Riverlane)
- Aleksander Kubica (Yale University)
- Nicolas Delfosse (IonQ)
- Andreas Wallraff (ETH Zürich)
- Matt McEwen (Google)
- Élie Gouzien (Alice & Bob)
Alice & Bob’s takeaways:
Harry Putterman (Senior Research Scientist, Amazon Web Services), “Hardware Efficient Quantum Error Correction Using Concatenated Bosonic Qubits”
Starting with hardware-efficient strategies, Harry presented Amazon’s recent work realizing quantum error correction with a cat qubit repetition code. Specifically, his talk showed how they are able to realize a distance-5 repetition code using transmon qubits as ancillas. In this hybrid cat-transmon architecture, they realize CNOT gates which have a noise bias against bit-flips. They are able to perform error correction to correct phase-flip errors while at the same time taking advantage of the cat qubits’ biased noise to minimize the introduction of bit-flip errors. The talk also discussed technical details enabling the experiment, such as carefully controlling nonlinearities in the cat qubits.
Harry outlined two possible paths with cat qubits: a hybrid transmon-cat system, and an approach with highly noise biased ancillas – like the one we’re pursuing at Alice and Bob.
Barbara Terhal (Professor, Delft University of Technology), “Lowering Connectivity Requirements for Bivariate Bicycle Codes Using Morphing Circuits”
Barbara introduced a way to make quantum error correction more efficient using morphing circuits. Google has already worked on a similar technique with surface code, and this work extends the framework to bivariate bicycle codes, introduced by IBM in 2024.
A pair of morphing circuits each shrinks half of the stabilizers of the code while expanding the rest to create two “end-cycle codes” from a “mid-cycle” code, providing useful parity check circuits for the end-cycle codes. This technique reduces connectivity requirements, which could help facilitate implementation on current hardware. It could also be a valuable tool for generating new code families by modifying existing ones using the morphing circuit scheme.
Theodore Yoder (IBM), “qLDPC Surgery Enables Scalable FTQC”
Quantum LDPC (qLDPC) codes are strong candidates for low-overhead, large-scale fault-tolerant quantum computing (FTQC), but they need flexible methods for fault-tolerant logical operations to compete with popular surface codes. For surface codes, lattice surgery is an essential tool for achieving FTQC.
Ted presented a method to make surgery-like operations work for arbitrary qLDPC codes without using many additional qubits. How does it work? They build an auxiliary system of qubits shaped by the logical Pauli to be measured. By measuring a specific set of Pauli check operators, the original qLDPC code is deformed onto this auxiliary system, effectively creating a new qLDPC code in which the target logical Pauli has been measured out. This approach creates the ability to perform logical multi-qubit gates on qLDPC codes and, with a supply of magic states, universal FTQC.
Aside from theoretical advances, IBM’s team also demonstrated several key hardware components for enabling the long-range on-chip interactions required for implementing qLDPC codes, including a 5×10⁻³ CNOT fidelity across a 14 mm coupler.
Earl Campbell (VP of Quantum Science, Riverlane), “Real-Time Decoding in Hardware”
QEC hinges on our ability to correct errors in real-time. Earl Campbell examined what real-time decoding really means, laying out 3 criteria he considers all platforms should satisfy:
1) No backlog – the system must process each error as soon as it shows up.
2) Low latency – The time between detecting an error and deciding how to fix it must be very short.
3) Fast feedback for classical control – once the system knows what error correction to apply, it must send that correction to the quantum computer immediately.
Earl’s conclusion? None of the current experimental implementations tick all the boxes yet, but this is the bar we should be aiming for.
He also gave a glimpse into Riverlane’s roadmap: move to decoding directly in hardware.
Aleksander Kubica (Assistant Professor of Applied Physics, Yale University), “Reducing the Overhead of Quantum Error Correction”
Aleksander’s talk addressed a major challenge in quantum computing: scalability. Quantum error correction demands huge hardware resources, so how can we make it more practical?
Aleksander discussed various strategies, including noise-biased qubits, erasure qubits, single shot QEC, algorithmic fault tolerance, and surface code architecture. One of our highlights: a new framework for running surface codes on chips with dead ancilla or data qubits. This scheme allows us to better preserve the distance of surface code on imperfect chips, improving logical error rates by orders of magnitude.
Nicolas Delfosse (Principal Researcher, IonQ), “Quantum Error Correction for Long Chains of Trapped Ions”
Nicolas’ talk made the case for ions as a strong contender for implementing qLDPC codes, offering both a near and long-term view.
For the near-term, he introduced a new take on error correction using Clifford Noise Reduction. Algorithms are broken into small chunks, run multiple times, and the results compared to spot errors. This allows for deeper circuits and offers a middle ground between noise mitigation and full error correction.
For the long term, he explored the implementation of quantum error correction codes with long chains of trapped ions, showing that the high connectivity of these systems allow for the implementation of quantum LDPC codes with few ancilla qubits.
Andreas Wallraff (Full Professor of Physics, ETH Zürich), “Performing Lattice Surgery on Two Distance-Three Repetition Codes Realized with Superconducting Qubits”
Andreas’ talk walked us through ETH Zürich’s recent experiment performing lattice surgery between two repetition codes, a key technique for implementing gates between logical qubits. They managed to prepare a Bell state between these two repetition codes, with 78.8% fidelity in error detection mode.
Their chip operates near the surface code threshold. One of the steps in the experiment was to implement a readout to detect leakage, a type of error which is highly detrimental to surface code. Like Google, the team will work on implementing a leakage reduction unit (LRU). Next, they plan to perform lattice surgery between two distance-three surface codes.
This kind of experiment speaks to the great progress in our field, as logical qubits move from a theoretical concept to reality.
Matt McEwen (Research Scientist, Google), “Demonstrating Dynamic Circuits”
Quantum error correction sits at the intersection of theory and experiment — and in his talk, Matt explored how this dynamic unfolded on Google’s Willow chip, which last year became the first to implement a below-threshold surface code.
Matt discussed the “dynamic circuit” point of view, where you are in a different code at each step of the circuit. At the circuit level, the right language to ensure fault-tolerance becomes the “detecting regions” rather than the stabilizers. This approach opens the door to the use of different gate sets. For experimentalists, this is good news! The usual CZ gate, for instance, introduces problematic leakage errors, while other gates like iSWAP are less noisy on transmons.
Élie Gouzien (Lead Scientist for Quantum Algorithms, Alice & Bob), “LDPC-cat codes for low overhead quantum computing in 2D“
Élie’s talk took us through Alice & Bob’s LDPC-cat architecture, which improves hardware efficiency by pairing cat qubits with classical LDPC codes. The usual repetition code doesn’t reach the BPT bound, a theoretical limit on how efficiently logical qubits can be encoded, for classical codes with a 2D connectivity. The LDPC-cat code helps improve this. The key idea is that cat qubits can be assembled into a 2D structure with local connectivity, enabling each physical qubit to contribute to several logical qubits, rather than just one. This means we can significantly reduce the number of physical qubits required, all while keeping the same error rate and number of logical qubits. This architecture could help us run large-scale algorithms with a far lower overhead, for example by 200x less for RSA-2048 factorization.
Where is fault-tolerance headed?
The road to FTQC is long—and every step demands close coordination between theorists and experimentalists. If there’s one thing this summit made even clearer, it’s that FTQC is an active, evolving engineering challenge being tackled from every angle. At Alice & Bob, we’ve always believed fault-tolerance will be key to making useful quantum computing a reality.
As the field pushes forward fast, peer collaboration will surely help us get there even faster!
We’re grateful to all the speakers and attendees who made this a standout event, and excited about what’s ahead. Stay curious!
